	US 12,394,713 B2
	Fabric die to fabric die interconnect for modularized integrated circuit devices
Chee Hak Teh, Bayan Lepas (MY); Chee Seng Leong, Gelugor (MY); Lai Guan Tang, Tanjung Bungah (MY); Han Wooi Lim, Bayan Lepas (MY); and Hee Kong Phoon, Bayan Lepas (MY)
Assigned to Altera Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 21, 2024, as Appl. No. 18/670,390.
Application 18/670,390 is a continuation of application No. 18/137,405, filed on Apr. 20, 2023, granted, now 12,009,298.
Application 18/137,405 is a continuation of application No. 17/131,464, filed on Dec. 22, 2020, granted, now 11,670,589, issued on Apr. 20, 2023.
Application 17/131,464 is a continuation of application No. 16/456,647, filed on Jun. 28, 2019, granted, now 10,886,218, issued on Jan. 5, 2021.
Prior Publication US 2024/0312909 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 23/498 (2006.01); H03K 19/17704 (2020.01)

CPC H01L 23/528 (2013.01) [H01L 23/49816 (2013.01); H03K 19/17704 (2013.01)]

20 Claims

1. A device comprising:

a first die comprising:

a first plurality of rows, wherein a first row of the first plurality of rows comprises:

a row of compute blocks;

a first inter-die interconnect interface coupled to a compute block of the row of compute blocks in the row of compute blocks; and

a first electrical connection electrically coupled to the first inter-die interconnect interface; and

a second die comprising:

a second plurality of rows, wherein a first row of the second plurality of rows comprises:

a row of memory blocks;

a second inter-die interconnect interface associated with the row of memory blocks; and

a second electrical connection electrically coupled to the second inter-die interconnect interface, wherein the first electrical connection and the second electrical connection are electrically coupled, and wherein the first inter-die interconnect interface and the second inter-die interconnect interface are configured to enable communication between the first die and the second die via the first electrical connection and the second electrical connection.

9. A die comprising:

a shoreline; and

a plurality of rows, wherein a row of the plurality of rows comprises:

a set of memory blocks separate from the shoreline of the die; and

an inter-die interconnect interface coupled via a set of microbumps to the set of memory blocks, wherein the inter-die interconnect interface is configured to communicatively couple the die to a second die.

18. A data processing system comprising:

a network interface;

a memory;

processing circuitry coupled to the network interface and the memory;

a first die comprising a first row comprising a first plurality of interconnect interfaces configured to electrically couple to a first plurality of electrical connections disposed on a side of the first die;

a second die comprising a second row comprising a second plurality of interconnect interfaces configured to electrically couple to a second plurality of electrical connections disposed on a side of the second die; and

a silicon interposer configured to electrically couple to the first plurality of electrical connections and the second plurality of electrical connections.