| CPC H01L 23/528 (2013.01) [H01L 23/535 (2013.01); H10B 43/27 (2023.02)] | 12 Claims |
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1. A method, comprising:
forming a stack of one or more material layers over a substrate of a memory die, the stack of one or more material layers comprising a layer of a conductive material;
forming, in a first region over the substrate, a plurality of memory cells;
forming one or more word line conductors over the substrate, each word line conductor of the one or more word line conductors operable to access one or more memory cells of the plurality of memory cells;
forming, in a second region over the substrate, a first island of the stack of one or more material layers based at least in part on removing the one or more material layers from a perimeter around the first island, wherein the first island is associated with a first dimension along a direction over the substrate;
forming, in a third region over the substrate that is between the first region and the second region along the direction over the substrate, a plurality of second islands of the stack of one or more material layers based at least in part on removing the one or more material layers from a perimeter around each second island, wherein each second island of the plurality of second islands is associated with a respective second dimension along the direction that is smaller than the first dimension; and
forming, in the second region over the first island, a plurality of electrical contacts extending along a thickness direction relative to the substrate, wherein each electrical contact of the plurality of electrical contacts is electrically coupled in the second region with a respective word line conductor of the one or more word line conductors, and wherein the conductive material of the first island is electrically floating.
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