| CPC H01L 23/5226 (2013.01) [H01L 23/28 (2013.01); H01L 23/3128 (2013.01); H01L 23/528 (2013.01); H01L 23/53238 (2013.01); H01L 24/14 (2013.01)] | 20 Claims |
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1. A method of manufacturing semiconductor package, comprising:
preparing a metal plate including a first metal layer, an etching barrier layer on the first metal layer, and a second metal layer on the etching barrier layer;
forming a pattern layer by etching a portion of the first metal layer;
attaching a tape carrier to the metal plate so that the pattern layer is embedded in the tape carrier;
forming a pillar layer by etching a portion of the second metal layer;
forming a barrier layer by etching a portion of the etching barrier layer between the pattern layer and the pillar layer;
disposing a semiconductor chip on the tape carrier so that a connection pad of the semiconductor chip is embedded in the tape carrier;
forming an encapsulant encapsulating the semiconductor chip, the pillar layer, and the barrier layer; and
after removing the tape carrier, forming a first redistribution structure including a first insulating layer covering the pattern layer and the connection pad, a first redistribution layer on the first insulating layer, and a first redistribution via penetrating through the first insulating layer and electrically connecting the first redistribution layer to the pattern layer and the connection pad.
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