US 12,394,707 B2
Back-end-of-line CMOS inverter having reduced size and reduced short-channel effects and methods of forming the same
Yun-Feng Kao, New Taipei (TW); and Katherine H. Chiang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 26, 2023, as Appl. No. 18/307,206.
Prior Publication US 2024/0363525 A1, Oct. 31, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76843 (2013.01); H01L 21/76879 (2013.01); H01L 23/5286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An inverter circuit, comprising:
a gate electrode formed over an interlayer dielectric layer;
a gate dielectric layer formed over the gate electrode;
a first-conductivity-type semiconductor layer formed over the gate dielectric layer;
a second-conductivity-type semiconductor layer formed over the gate dielectric layer, laterally displaced and isolated from the first-conductivity-type semiconductor layer;
a first source electrode formed in contact with the first-conductivity-type semiconductor layer;
a second source electrode formed in contact with the second-conductivity-type semiconductor layer; and
a shared drain electrode formed in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer.