US 12,394,705 B2
Layout design of custom stack capacitor to procure high capacitance
Prakash Rattaisutripalayam Palanisamy, Bangalore (IN); Bruce Lee, Irvine, CA (US); Bavireddy Sai Krishna, Guntur (IN); and Balavva Shivappa Kamatagi, Bailhongal (IN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 15, 2022, as Appl. No. 17/888,369.
Prior Publication US 2024/0055346 A1, Feb. 15, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 1/68 (2025.01); H10D 84/80 (2025.01)
CPC H01L 23/5223 (2013.01) [H01L 23/528 (2013.01); H10D 1/714 (2025.01); H10D 84/813 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A chip, comprising:
a first capacitor comprising:
first electrodes formed from metal layer M0, wherein the first electrodes are coupled to one another;
second electrodes formed from the metal layer M0, wherein the second electrodes are coupled to one another;
wherein each of the first electrodes and each of the second electrodes extends in a first direction,
a first one of the first electrodes and a second one of the first electrodes are separated by a first gap in the first direction,
a third one of the first electrodes and a fourth one of the first electrodes are separated by a second gap in the first direction,
a first portion of one of the second electrodes is between the first one of the first electrodes and the third one of the first electrodes, and
a second portion of the one of the second electrodes is between the second one of the first electrodes and the fourth one of the first electrodes;
one or more vias disposed on a third portion of the one of the second electrodes, wherein the third portion of the one of the second electrodes is between the first portion of the one of the second electrodes and the second portion of the one of the second electrodes;
a first metal routing formed from metal layer M1, wherein the first metal routing is coupled to the first one of the first electrodes and the third one of the first electrodes;
a second metal routing formed from the metal layer M1, wherein the second metal routing is coupled to the second one of the first electrodes and the fourth one of the first electrodes; and
a third metal routing formed from the metal layer M1, wherein the one or more vias are coupled between the one of the second electrodes and the third metal routing, wherein
the first metal routing and the third metal routing are located on opposite sides of a first gate, and
the third metal routing and the second metal routing are located on opposite sides of a second gate.