US 12,394,701 B2
Semiconductor package including a redistribution substrate and a method of fabricating the same
Sang-Uk Kim, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 21, 2024, as Appl. No. 18/612,193.
Application 18/612,193 is a continuation of application No. 17/562,157, filed on Dec. 27, 2021, granted, now 11,961,793.
Claims priority of application No. 10-2021-0059383 (KR), filed on May 7, 2021.
Prior Publication US 2024/0266268 A1, Aug. 8, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 23/3107 (2013.01); H01L 23/49827 (2013.01); H01L 25/0652 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13118 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/013 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first re-distribution layer;
a second re-distribution layer on the first re-distribution layer and vertically spaced apart from the first re-distribution layer;
a first semiconductor chip on a top surface of the first re-distribution layer;
a first connection chip on a bottom surface of the first re-distribution layer;
a second connection chip on a top surface of the second re-distribution layer;
a conductive structure and mold layer between the first re-distribution layer and the second re-distribution layer, and
a first lower semiconductor chip on a bottom surface of the second re-distribution layer,
wherein:
the mold layer surrounds the first connection chip, the second connection chip and the conductive structure, and
the conductive structure is spaced apart from the first connection chip and the second connection chip in a first direction parallel to the top surface of the first re-distribution layer,
wherein the second connection chip is of a plurality of second connection chips, wherein the plurality of second connection chips are spaced apart from each other along the first direction.