US 12,394,700 B2
Semiconductor package
Dongkyu Kim, Anyang-si (KR); Seokhyun Lee, Hwaseong-si (KR); Kyoung Lim Suk, Suwon-si (KR); Jaegwon Jang, Hwaseong-si (KR); and Gwangjae Jeon, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 28, 2023, as Appl. No. 18/374,396.
Application 18/374,396 is a continuation of application No. 17/177,305, filed on Feb. 17, 2021, granted, now 11,804,427.
Claims priority of application No. 10-2020-0076011 (KR), filed on Jun. 22, 2020.
Prior Publication US 2024/0030119 A1, Jan. 25, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 23/49833 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first redistribution substrate having a first surface and a second surface, which are opposite to each other;
a first semiconductor chip on the first surface of the first redistribution substrate; and
an outer coupling terminal on the second surface of the first redistribution substrate,
wherein the first redistribution substrate comprises:
a first insulating layer;
a first redistribution pattern in the first insulating layer, and includes an interconnection portion and a via portion; and
an under-bump pattern between the outer coupling terminal and the interconnection portion of the first redistribution pattern,
wherein the under-bump pattern has a third surface and a fourth surface, which are opposite to each other,
wherein the third surface of the under-bump pattern is in direct physical contact with the interconnection portion of the first redistribution pattern, and
wherein the first insulating layer is in direct physical contact with an edge portion of the fourth surface of the under-bump pattern.