US 12,394,683 B2
Molded semiconductor chip package with stair-step molding layer
Priyal Shah, San Jose, CA (US); Rahul Agarwal, Livermore, CA (US); Milind S. Bhagavat, Broomfield, CO (US); and Chia-Hao Cheng, Hsinchu (TW)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Mar. 18, 2020, as Appl. No. 16/822,353.
Prior Publication US 2021/0296194 A1, Sep. 23, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3128 (2013.01) [H01L 21/3043 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3121 (2013.01); H01L 24/96 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor chip package, comprising:
a routing substrate;
a semiconductor chip mounted on and electrically connected to the routing substrate, the semiconductor chip having plural side surfaces;
another semiconductor chip having plural other side surfaces mounted on the routing substrate;
an underfill between the routing substrate and the semiconductor chip; and
a molding layer at least partially encasing the semiconductor chip, the molding layer having a tread and a riser, the riser abutting at least some of the plural side surfaces of the semiconductor chip and at least some of the plural other side surfaces of the another semiconductor chip, wherein a top surface of the tread is higher than a top surface of the underfill, and wherein a top surface of the riser abuts the at least some of the plural side surfaces of the semiconductor chip, and wherein a portion of the top surface of the tread laterally overlaps and is positioned over a top edge of the underfill.