US 12,394,676 B2
Semiconductor package structure and method for manufacturing the same
Chen-Chao Wang, Kaohsiung (TW); Chih-Yi Huang, Kaohsiung (TW); and Keng-Tuan Chang, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Feb. 12, 2024, as Appl. No. 18/439,743.
Application 18/439,743 is a continuation of application No. 17/893,033, filed on Aug. 22, 2022, granted, now 11,901,245.
Application 17/893,033 is a continuation of application No. 17/067,565, filed on Oct. 9, 2020, granted, now 11,424,167.
Prior Publication US 2024/0186193 A1, Jun. 6, 2024
Int. Cl. H01L 21/66 (2006.01); H01L 23/485 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 22/22 (2013.01) [H01L 23/485 (2013.01); H01L 23/49838 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a plurality of first electrical contacts, wherein a first imaginary line extends through a row of the plurality of first electrical contacts;
a plurality of second electrical contacts disposed outside the first imaginary line, wherein a second imaginary line extends through a row of the plurality of second electrical contacts, and the first imaginary line is non-parallel with the second imaginary line in a top view; and
an interconnection structure connecting the plurality of first electrical contacts and the plurality of second electrical contacts, wherein in a cross section view, the plurality of first electrical contacts laterally overlap the plurality of second electrical contacts, wherein the interconnection structure includes a trace including two segments intersecting with each other at an intersection angle.