US 12,394,674 B2
Method and machine for examining wafers
Chien-Hung Chou, San Jose, CA (US); and Wen-Tin Tai, Fremont, CA (US)
Assigned to ASML Netherlands B.V., Veldhoven (NL)
Filed by ASML Netherlands B.V., Veldhoven (NL)
Filed on Nov. 13, 2020, as Appl. No. 17/097,063.
Application 17/097,063 is a continuation of application No. 15/708,060, filed on Sep. 18, 2017, granted, now 10,840,156.
Application 15/708,060 is a continuation of application No. 13/589,378, filed on Aug. 20, 2012, granted, now 9,768,082, issued on Sep. 19, 2017.
Application 13/589,378 is a continuation in part of application No. 12/370,913, filed on Feb. 13, 2009, abandoned.
Prior Publication US 2021/0193537 A1, Jun. 24, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G05B 19/418 (2006.01); H01L 21/66 (2006.01); G01N 21/88 (2006.01); G01N 21/95 (2006.01)
CPC H01L 22/20 (2013.01) [G05B 19/41875 (2013.01); G01N 2021/8861 (2013.01); G01N 2021/8867 (2013.01); G01N 21/9501 (2013.01); G05B 2219/32205 (2013.01); G05B 2219/37224 (2013.01); Y02P 90/02 (2015.11); Y02P 90/80 (2015.11)] 23 Claims
OG exemplary drawing
 
1. An inspection apparatus for inspecting a semiconductor wafer, the inspection apparatus comprising:
a high resolution imaging tool comprising a source configured to provide a beam for imaging a semiconductor pattern on the semiconductor wafer;
a memory storing a set of instructions; and
a processor configured to execute the set of instructions to cause the apparatus to:
determine a similarity between a map representing the semiconductor wafer and a reference;
determine a first inspecting plan for inspecting the semiconductor wafer according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
acquire at least one image of the semiconductor pattern on the semiconductor wafer with the high resolution imaging tool using the first inspecting plan;
identify semiconductor fabrication defects in the inspection area according to the at least one image;
in response to the similarity exceeding a threshold, set a semiconductor wafer map flag value to a first value, or in response to the similarity not exceeding the threshold, set the semiconductor wafer map flag value to a second value; and
construct the first inspecting plan when the semiconductor wafer map flag is the first value, or construct a second inspecting plan when the semiconductor wafer map flag is the second value.