US 12,394,667 B2
Bit line spacer structures including air gaps and method for forming the same
Daejoong Won, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 12, 2022, as Appl. No. 17/650,843.
Application 17/650,843 is a continuation of application No. PCT/CN2021/117092, filed on Sep. 8, 2021.
Claims priority of application No. 202110767947.5 (CN), filed on Jul. 7, 2021.
Prior Publication US 2023/0009103 A1, Jan. 12, 2023
Int. Cl. H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76825 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76885 (2013.01); H10B 12/482 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
providing a base, on which multiple discrete conductive connection structures are formed;
forming sacrificial side walls on side walls of the conductive connection structures;
forming an outer side wall material layer on surfaces of the sacrificial side walls;
perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls; wherein the perforating is performed by ion implantation; and when the ion implantation is performed, parts of the outer side wall material layer are removed by implanted ions through bombardment and/or chemical reaction, to form the pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls;
removing the sacrificial side walls through the pinholes to form air gaps; and
forming a cover layer for sealing the pinholes.