| CPC H01L 21/76816 (2013.01) [H01L 21/31144 (2013.01); H10B 43/27 (2023.02); H10B 43/50 (2023.02)] | 19 Claims |
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1. A method of manufacturing a semiconductor device, the method comprising:
forming an etching target layer on a substrate;
forming a first photoresist layer on the etching target layer;
forming a first alignment key under the first photoresist layer and a first alignment pattern aligned in a first direction perpendicular to a top surface of the substrate, by exposing and developing the first photoresist layer;
forming a second alignment key under the first photoresist layer and a second alignment pattern aligned in the first direction, by exposing and developing the first photoresist layer; and
forming a third alignment key aligned with the first alignment key in the first direction under the first photoresist layer and a fourth alignment key aligned with the second alignment key in the first direction on the etching target layer based on the first and second alignment patterns,
wherein a distance between the first alignment pattern and the first photoresist layer in the first direction is different than a distance between the second alignment pattern and the first photoresist layer in the first direction.
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10. A method of manufacturing a semiconductor device, the method comprising:
forming a peripheral transistor, a first conductive pattern electrically connected to the peripheral transistor, and a first alignment key at the same level as the first conductive pattern on a substrate;
forming a mold and a first upper insulating layer, wherein the mold comprises a plurality of sacrificial layers and a plurality of insulating layers alternately stacked on the substrate and the first upper insulating layer covers at least part of the mold;
forming a plurality of channel structures that vertically penetrate the mold and a second alignment key that vertically penetrates the first upper insulating layer;
removing the plurality of sacrificial layers and forming a plurality of gate electrodes in a residual space from which the plurality of sacrificial layers are removed;
forming a second upper insulating layer on the first upper insulating layer;
forming a first photoresist layer on the second upper insulating layer;
forming a first alignment pattern vertically aligned with the first alignment key on the first photoresist layer;
forming a second alignment pattern vertically aligned with the second alignment key on the first photoresist layer; and
forming third and fourth alignment keys on the second upper insulating layer by using the first photoresist layer on which the first and second alignment patterns are formed, as an etching mask.
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15. A method of manufacturing a semiconductor device, the method comprising:
forming a peripheral transistor, a first conductive pattern electrically connected to the peripheral transistor, and a first alignment key at the same level as the first conductive pattern on a substrate;
forming a mold and a first upper insulating layer, wherein the mold comprises a plurality of sacrificial layers and a plurality of insulating layers that are alternately stacked on the substrate and the first upper insulating layer covers at least part of the mold;
forming a plurality of channel structures that vertically penetrate the mold and a second alignment key that vertically penetrates the first upper insulating layer;
removing the plurality of sacrificial layers and forming a plurality of gate electrodes in a space from which the plurality of sacrificial layers are removed;
forming a second upper insulating layer on the first upper insulating layer; and
forming third and fourth alignment keys on the second upper insulating layer,
wherein the third alignment key is vertically aligned with the first alignment key,
wherein the fourth alignment key is vertically aligned with the second alignment key, and
wherein the third and fourth alignment keys are formed substantially at the same time.
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