US 12,394,660 B2
Buried power rail after replacement metal gate
Devika Sarkar Grant, Rensselaer, NY (US); Sagarika Mukesh, Albany, NY (US); Kisik Choi, Watervliet, NY (US); Somnath Ghosh, Clifton Park, NY (US); and Ruilong Xie, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 22, 2021, as Appl. No. 17/531,837.
Prior Publication US 2023/0163020 A1, May 25, 2023
Int. Cl. H10D 30/62 (2025.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/743 (2013.01) [H01L 21/76879 (2013.01); H01L 23/5286 (2013.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first source/drain (S/D) connected to a first field-effect transistor (FET) region;
a second S/D connected to a second FET region;
a buried power rail (BPR) region extending laterally in a first direction, and located between the first FET region and the second FET region, comprising:
a buried power rail (BPR);
a first dielectric liner lining a first lateral side of the BPR region, wherein the first dielectric liner isolates the BPR from the first FET region and the first S/D;
a second dielectric liner lining a second lateral side of the BPR region, wherein the second dielectric liner isolates the BPR from the second FET region; and
a contact electrically connecting the second S/D and the BPR through the second lateral side of the BPR region, wherein the first dielectric liner extends higher than the second dielectric liner in the BPR region.