US 12,394,606 B2
Impedance control of local areas of a substrate during plasma deposition thereon in a large PECVD chamber
Zheng John Ye, Santa Clara, CA (US); Andrew C. Lam, San Francisco, CA (US); Zeqiong Zhao, Santa Clara, CA (US); Jianhua Zhou, Campbell, CA (US); Hshiang An, Santa Clara, CA (US); Suhail Anwar, Saratoga, CA (US); Yoshitake Nakajima, Santa Clara, CA (US); and Fu-Ting Chang, Tainan (TW)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Oct. 21, 2022, as Appl. No. 17/971,205.
Prior Publication US 2024/0136160 A1, Apr. 25, 2024
Prior Publication US 2024/0234105 A9, Jul. 11, 2024
Int. Cl. H01J 37/32 (2006.01); C23C 16/458 (2006.01); C23C 16/505 (2006.01); C23C 16/52 (2006.01)
CPC H01J 37/32715 (2013.01) [C23C 16/4586 (2013.01); C23C 16/505 (2013.01); C23C 16/52 (2013.01); H01J 37/321 (2013.01); H01J 37/32183 (2013.01); H01J 2237/0262 (2013.01); H01J 2237/20235 (2013.01); H01J 2237/24564 (2013.01); H01J 2237/3321 (2013.01); H01J 2237/3323 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A plasma processing system, comprising:
a substrate support disposed within a processing volume of the plasma processing system, the substrate support comprising a body having a plurality of openings formed between a substrate support surface and backside opposite the substrate support surface;
a plurality of substrate support pins deposed in the plurality of openings of the substrate support, wherein when the substrate support is in a raised position, top portions of the plurality of substrate support pins are planar with or recessed below the substrate support surface, and when in a lowered position the substrate support pins extend above the substrate support surface;
a plurality of adjustable impedance circuits in electrical communications with associated ones of the plurality of substrate support pins; and
radio frequency (RF) voltage and RF current detectors electrically coupled to each of the plurality of adjustable impedance circuits.