US 12,394,501 B2
Apparatus with adjustable diagnostic mechanism and methods for operating the same
Takuya Tamano, Boise, ID (US); Yoshinori Fujiwara, Boise, ID (US); and Daniel S. Miller, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 20, 2023, as Appl. No. 18/137,388.
Claims priority of provisional application 63/389,463, filed on Jul. 15, 2022.
Prior Publication US 2024/0021262 A1, Jan. 18, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A memory device, comprising:
a memory array including memory cells configured to store data and provide access to the stored data;
a multiple input signature register (MISR) circuit configured to collect and process a set of self-test results; and
a memory built-in self-test (mBIST) circuit coupled to the MISR circuit and the memory array, the BIST circuit configured to implement a self-test for the memory and generate the set of self-test results,
wherein the self-test corresponds to (1) writing predetermined data and (2) reading the written data using one or more known locations in the memory array to test functionalities of the memory array, and
wherein implementing the self-test includes deactivating the MISR circuit during one or more portions of the self-test to suspend collection and/or processing of self-test outputs self-test outputs during the one or more portions.