| CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01)] | 15 Claims |
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1. An antifuse-type non-volatile memory, comprising:
an antifuse-type memory cell array comprising a first memory cell, wherein the first memory cell is connected with an antifuse control line, a first word line and a first bit line, and the first memory cell comprises an antifuse transistor and a select transistor, wherein a first drain/source terminal of the select transistor is connected with the first bit line, a gate terminal of the select transistor is connected with the first word line, a first drain/source terminal of the antifuse transistor is coupled to a second drain/source terminal of the select transistor, and a gate terminal of the antifuse transistor is connected with the antifuse control line; and
a control circuit comprising:
an oscillator generating a clock signal;
a program voltage generator comprising a charge pump, wherein the charge pump is connected with the oscillator to receive the clock signal, wherein when a program action is performed, a supply voltage is boosted to a program voltage by the charge pump according to the clock signal, and the program voltage is provided to the antifuse control line;
a timing controller connected with the oscillator, wherein the timing controller receives the clock signal and generates a timing control signal;
a word line driver connected with the first word line of the antifuse-type memory cell array, wherein the word line driver is connected with the timing controller to receive the timing control signal; and
a bit line driver connected with the first bit line of the antifuse-type memory cell array, wherein in a program cycle of the program action, the first word line is activated by the word line driver, and the first bit line is activated by the bit line driver, so that the first memory cell is a selected memory cell,
wherein in the program cycle of the program action, the word line driver issues a pulse signal to the first word line according to the timing control signal, wherein a first level of the pulse signal is an on voltage, and a second level of the pulse signal is an off voltage, wherein after the program cycle, a storage state of the first memory cell is switched from a high-resistance storage state to a low-resistance storage state.
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