| CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01)] | 7 Claims |
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1. A memory device comprising:
a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines;
a control circuit suitable for repeatedly performing a plurality of program loops until programming for a selected word line among the plurality of word lines is completed; and
wherein the control circuit performs the following in each of the program loops:
generates any one of N types of column voltages according to values of N types of M-bit setting codes input to a page buffer, and applies the generated column voltage to each of a plurality of bit lines, in a bit line setup operation,
applies a program voltage for the selected word line in a program voltage application operation,
applies (N−1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line in a verification operation, and
determines the values of the N types of M-bit setting codes to be input to the page buffer in the bit line setup operation of a subsequent program loop, on the basis of a result of the application of the (N−1) first verification voltages to the selected word line according to the predetermined order,
wherein “N” is a natural number equal to or greater than 4, and “M” is a natural number equal to or greater than 2.
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