US 12,394,497 B2
Efficient bitline stabilization for program inhibit in NAND arrays
Tarek Ahmed Ameen Beshari, San Jose, CA (US); Shantanu R. Rajwade, San Mateo, CA (US); Ahsanur Rahman, Folsom, CA (US); Sagar Upadhyay, Folsom, CA (US); and Pratyush Chandrapati, Folsom, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Dec. 23, 2023, as Appl. No. 18/395,541.
Prior Publication US 2024/0136003 A1, Apr. 25, 2024
Int. Cl. G06F 12/00 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A storage device comprising:
a nonvolatile storage medium having storage cells coupled to bitlines; and
a media controller to generate a control signal after performing a program verify, to connect bitlines of the nonvolatile storage medium to an external regulator instead of an internal regulator to charge the bitlines, and then to connect the bitlines to the internal regulator to prepare the bitlines for a program pulse.