US 12,394,492 B2
Memory cell sensing circuit with adjusted bias from pre-boost operation
Shantanu R. Rajwade, Santa Clara, CA (US); Bayan Nasri, Folsom, CA (US); Tzu-Ning Fang, Palo Alto, CA (US); Rezaul Haque, Folsom, CA (US); Dhanashree R. Kulkarni, El Dorado Hills, CA (US); Narayanan Ramanan, San Jose, CA (US); Matin Amani, Fremont, CA (US); Ahsanur Rahman, Folsom, CA (US); Seong Je Park, San Jose, CA (US); and Netra Mahuli, Folsom, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Nov. 30, 2020, as Appl. No. 17/107,679.
Prior Publication US 2022/0172784 A1, Jun. 2, 2022
Int. Cl. G11C 16/26 (2006.01); G11C 13/00 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 13/004 (2013.01); G11C 16/0483 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A sense circuit comprising:
an output transistor to drive a sense output;
a sense node to drive a gate of the output transistor based on a value read from a memory cell;
a precharge circuit to precharge the sense node and the gate of the output transistor to a voltage reference prior to a sense operation; and
a boost circuit to boost the sense node, the boost circuit to be boosted up by a first boost voltage during precharge in which the sense node is precharged to the voltage reference, and the boost circuit to boost up the sense node after precharge to increase the voltage of the sense node by a second boost voltage greater than the first boost voltage, and discharge the sense node after the sense operation by a combination of the first boost voltage and the second boost voltage.