US 12,394,491 B2
Apparatus and method for selectively reducing charge pump speed during erase operations
Abu Naser Zainuddin, San Ramon, CA (US); Jiahui Yuan, Fremont, CA (US); Mark Shlick, Ganey-Tikva (IL); and Shemmer Choresh, Tel-Aviv (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 19, 2023, as Appl. No. 18/355,352.
Claims priority of provisional application 63/481,887, filed on Jan. 27, 2023.
Prior Publication US 2024/0257878 A1, Aug. 1, 2024
Int. Cl. G11C 16/14 (2006.01); G11C 5/14 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 5/145 (2013.01); G11C 16/32 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of non-volatile memory cells;
a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells; and
a control circuit coupled to the non-volatile memory cells and the charge pump circuit, the control circuit configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal based on a memory operation being performed on the non-volatile memory cells
wherein the non-volatile memory cells are disposed in a plurality of integrated circuit die; and
wherein the control circuit is further configured to selectively reduce the clock rate based on a number of the integrated circuit die that are operating in parallel.