US 12,394,487 B2
Method of programming data in nonvolatile memory device and nonvolatile memory device performing the same
Hyun Seo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 11, 2023, as Appl. No. 18/464,383.
Claims priority of application No. 10-2022-0181303 (KR), filed on Dec. 22, 2022.
Prior Publication US 2024/0212761 A1, Jun. 27, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/04 (2006.01); G11C 7/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming data in a nonvolatile memory device including a plurality of memory cells and a page buffer configured to control the plurality of memory cells, wherein the plurality of memory cells are electrically connected to a plurality of wordlines and a plurality of bitlines, the method comprising:
in a first program time period of a first program loop, applying a program voltage having a first program voltage to a selected wordline that is electrically connected to a target memory cell on which a program operation is performed; and
in the first program time period, applying a bitline shut-off signal having a first delay to the page buffer,
wherein the program voltage is applied to the selected wordline multiple times during one program loop while a magnitude of the program voltage is changed for each of the multiple times that the program voltage is applied,
wherein, as the magnitude of the program voltage increases, a delay of the bitline shut-off signal increases, and
wherein the delay of the bitline shut-off signal corresponds to a time period during which the bitline shut-off signal maintains a ground voltage.