US 12,394,485 B2
Integrated circuit structure and method for operating the same
Yu-Yu Lin, New Taipei (TW); and Feng-Min Lee, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/519,156.
Prior Publication US 2025/0174273 A1, May 29, 2025
Int. Cl. G11C 16/16 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 5/063 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure (IC structure), comprising:
a substrate; and
a first resistive memory string over the substrate and comprising a plurality of memory cells, each of the memory cells comprising:
a word line transistor comprising a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region; and
a resistor over the word line transistor and being electrically connected with the word line transistor in parallel,
wherein the word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.