US 12,394,482 B2
Semiconductor memory device and manufacturing method thereof
Ippei Kume, Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 4, 2022, as Appl. No. 17/687,085.
Claims priority of application No. 2021-152185 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0088551 A1, Mar. 23, 2023
Int. Cl. H01L 27/11524 (2017.01); G11C 16/04 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first memory cell chip including:
a plurality of first conductive layers arranged at intervals in a first direction,
first insulators alternately arranged with respect to the plurality of first conductive layers in the first direction,
a first semiconductor layer extending in the first direction through the plurality of first conductive layers,
a first insulating film disposed between the first semiconductor layer and the plurality of first conductive layers,
a first source line extending in a second direction perpendicular to the first direction to be in contact with a plural number of the first semiconductor layers and a plural number of the first insulating films, and
a first electrode disposed in contact with an upper side of the first source line; and
a second memory cell chip including:
a second electrode in contact with the first electrode, and
a second source line extending in the second direction and in contact with the second electrode.