US 12,394,479 B2
PMOS voltage selection circuit with an auxiliary selection circuit to prevent a floating output
Yu-Ping Huang, Hsinchu County (TW); Chun-Hung Lin, Hsinchu County (TW); and Cheng-Da Huang, Hsinchu County (TW)
Assigned to eMemory Technology Inc., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on May 9, 2023, as Appl. No. 18/144,858.
Claims priority of provisional application 63/388,258, filed on Jul. 12, 2022.
Prior Publication US 2024/0021246 A1, Jan. 18, 2024
Int. Cl. G11C 16/30 (2006.01); G11C 5/14 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/0433 (2013.01) [G11C 16/30 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A selection circuit comprising:
a main selection circuit comprising:
a first main transistor comprising:
a first terminal coupled to a first voltage terminal;
a control terminal coupled to a second voltage terminal; and
a second terminal and a bulk terminal coupled to an output terminal; and
a second main transistor comprising:
a first terminal coupled to the second voltage terminal;
a control terminal coupled to the first voltage terminal; and
a second terminal and a bulk terminal coupled to the output terminal; and
an auxiliary selection circuit comprising
a first auxiliary transistor comprising:
a control terminal;
a first terminal coupled to the first voltage terminal; and
a second terminal and a bulk terminal coupled to the output terminal;
a second auxiliary transistor comprising:
a control terminal coupled to the control terminal of the first auxiliary transistor;
a first terminal coupled to the second voltage terminal; and
a second terminal and a bulk terminal coupled to the output terminal;
a third auxiliary transistor comprising:
a control terminal coupled to the second voltage terminal;
a first terminal coupled to the first voltage terminal; and
a second terminal and a bulk terminal directly coupled to the control terminal of the first auxiliary transistor; and
a fourth auxiliary transistor comprising:
a control terminal coupled to the first voltage terminal;
a first terminal coupled to the second voltage terminal; and
a second terminal and a bulk terminal directly coupled to the control terminal of the first auxiliary transistor.