US 12,394,476 B2
In-memory computing (IMC) memory device and in-memory computing method
Yu-Yu Lin, New Taipei (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Nov. 8, 2023, as Appl. No. 18/504,254.
Prior Publication US 2025/0149083 A1, May 8, 2025
Int. Cl. G11C 11/4096 (2006.01); G11C 11/404 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4045 (2013.01); G11C 11/4076 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An in-memory computing (IMC) memory device, comprising:
a memory control circuit; and
a memory array coupled to the memory control circuit, the memory array including:
a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings, the plurality of computing memory cells storing a plurality of weight values;
a loading capacitor coupled to the plurality of computing memory cells; and
a measurement circuit coupled to the loading capacitor,
wherein in programming, the memory control circuit determines a first resistance state number of the balance computing memory cells of the memory string based on a first resistance state number of the computing memory cells of the memory string;
wherein in IMC operations,
a plurality of input voltages are input into the plurality of computing memory cells, the plurality of input voltages being corresponding to a plurality of input values, the memory control circuit sets the plurality of input values based on the plurality of input voltages,
a plurality of balance input voltages are input into the plurality of balance computing memory cells, the plurality of balance input voltages being corresponding to a plurality of balance input values, the plurality of balance input voltages are enable input values, the memory control circuit sets the plurality of balance input values based on the plurality of balance input voltages,
a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values,
when a read voltage is applied to the plurality of computing memory cells, the plurality of computing memory cells generate a plurality of cell currents, the plurality of cell currents are summed into a plurality of memory string currents,
the plurality of memory string currents from the plurality of memory strings charge the loading capacitor,
the measurement circuit measures a capacitor voltage of the loading capacitor, and
based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the plurality of input values and the plurality of weight values is determined.