US 12,394,475 B2
Memory device and method for adjusting logic states of data strobe signals used by memory device
Wu-Der Yang, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Oct. 23, 2023, as Appl. No. 18/382,659.
Prior Publication US 2025/0131956 A1, Apr. 24, 2025
Int. Cl. G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array;
a control circuit, configured to control data access of the memory cell array; and
an interface circuit, configured to receive a write command, a first data strobe signal, and a second data strobe signal from a memory controller, wherein the interface circuit comprises:
a receiver circuit, configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal;
wherein in response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to adjust a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal,
wherein the control circuit is further configured to perform a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.