US 12,394,473 B2
Interface of a memory circuit
Wenliang Chen, Hsinchu County (TW); Girish Nanjappa, Hsinchu County (TW); Lin Ma, Hsinchu County (TW); Hung-Piao Ma, Hsinchu County (TW); Keng Lone Wong, Hsinchu County (TW); and Chun Yi Lin, Hsinchu County (TW)
Assigned to AP MEMORY TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed by AP MEMORY TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed on Dec. 11, 2023, as Appl. No. 18/535,112.
Application 18/535,112 is a continuation of application No. 17/529,709, filed on Nov. 18, 2021, granted, now 11,842,763.
Claims priority of provisional application 63/118,621, filed on Nov. 25, 2020.
Prior Publication US 2024/0112727 A1, Apr. 4, 2024
Int. Cl. G11C 11/4076 (2006.01); G09G 3/20 (2006.01); G09G 3/3208 (2016.01); G11C 11/4093 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/4093 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3208 (2013.01); G11C 11/4076 (2013.01); G11C 11/419 (2013.01); G09G 2330/021 (2013.01); G09G 2330/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interface of a memory circuit comprising:
a chip enable terminal configured to receive a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit;
at least one data terminal configured to receive at least one first data terminal signal that varies between a second high voltage and the low voltage during a command phase, and to transmit or receive at least one second data terminal signal during a data phase; and
a data strobe terminal configured to receive a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and to transmit or receive a second data strobe signal that swings periodically between two different voltages during the data phase;
wherein during a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically between the two different voltages.