US 12,394,472 B2
Memory device and method for operating the same
Chien Yu Chen, New Taipei (TW); and Po-Jen Yang, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Dec. 26, 2023, as Appl. No. 18/396,210.
Prior Publication US 2025/0210097 A1, Jun. 26, 2025
Int. Cl. G11C 11/4093 (2006.01); G11C 17/16 (2006.01); H03K 19/00 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 17/16 (2013.01); H03K 19/0005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory circuit;
a redistribution layer coupled to the memory circuit; and
a resistor circuit coupled to the memory circuit and comprising a first resistor set and a second resistor set,
wherein the first resistor set comprises a first resistor and a second resistor,
the second resistor set comprises a third resistor and a fourth resistor, and
after the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel according to an impedance value of the redistribution layer, the first resistor set and the second resistor set are coupled in parallel according to an impedance value of the memory circuit.