US 12,394,469 B2
DRAM computation circuit and method
Chieh Lee, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Yi-Ching Liu, Hsinchu (TW); Wen-Chang Cheng, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 14, 2024, as Appl. No. 18/743,950.
Application 18/743,950 is a continuation of application No. 17/589,729, filed on Jan. 31, 2022, granted, now 12,014,768.
Claims priority of provisional application 63/226,902, filed on Jul. 29, 2021.
Prior Publication US 2024/0331760 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 5/063 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a boundary layer;
a first circuit positioned on a first side of the boundary layer and comprising a dynamic random-access memory (DRAM) array, wherein the DRAM array comprises a plurality of DRAM cells;
a second circuit positioned on a second side of the boundary layer opposite the first side and comprising a computation circuit, wherein the computation circuit comprises a sense amplifier circuit; and
a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit, wherein each bit line of the plurality of bit lines comprises a via structure positioned in the boundary layer,
wherein the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.