US 12,394,468 B2
Row hammer mitigation using hierarchical detectors
Edmund J. Gieske, Cedar Park, TX (US); Cagdas Dirik, Indianola, WA (US); and Robert M. Walker, Raleigh, NC (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 1, 2023, as Appl. No. 18/204,786.
Claims priority of provisional application 63/348,374, filed on Jun. 2, 2022.
Prior Publication US 2023/0395126 A1, Dec. 7, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/4078 (2006.01)
CPC G11C 11/4078 (2013.01) [G11C 11/40618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a number of memory devices; and
a memory controller coupled to one or more of the number of memory devices, the memory controller including, interface management circuitry, a first row hammer detector; and
a second row hammer detector;
and wherein the memory controller is configured to:
receive signaling indicative of a row activation command and a row address;
increment a row counter corresponding to the row address stored in a data structure of the first row hammer detector coupled to the controller;
determine that the incremented row counter is greater than a row hammer threshold (RHT); and
responsive to determining that the incremented row counter is greater than the first RHT, issue a row hammer mitigation command to perform row hammer detection with the second row hammer detector.