US 12,394,467 B2
Read clock start and stop for synchronous memories
Aaron John Nygren, Boise, ID (US); Karthik Gopalakrishnan, Cupertino, CA (US); and Tsun Ho Liu, Boston, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,499.
Claims priority of provisional application 63/287,151, filed on Dec. 8, 2021.
Prior Publication US 2023/0178138 A1, Jun. 8, 2023
Int. Cl. G11C 11/40 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 3/06 (2006.01); G11C 11/4076 (2006.01); G06F 1/3234 (2019.01); G06F 1/3237 (2019.01); G06F 12/00 (2006.01); G06F 13/00 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0671 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); G06F 12/00 (2013.01); G06F 13/00 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory, comprising:
a read clock circuit having an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal; and
a mode register that provides said read clock mode signal in response to a read clock mode,
wherein said read clock circuit provides said hybrid read clock signal:
as a free-running clock signal that toggles continuously when said read clock mode is a first mode; and
as a strobe signal that is active only in response to the memory receiving a read command and that stops toggling after a postamble period when said read clock mode is a second mode.