| CPC G11C 11/40622 (2013.01) [G11C 11/40611 (2013.01); G11C 11/4078 (2013.01)] | 20 Claims |

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1. A memory device, comprising:
a memory cell array including a plurality of memory cells coupled to wordlines and bitlines;
a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array;
a register configured to store the weighted access count for each of a plurality of row addresses;
an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, the access spacing being based on a first access and a subsequent access of a target row of the memory device; and
a calculator configured to calculate the access spacing.
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