US 12,394,464 B2
Hybrid FeRAM/OxRAM data storage circuit
Michele Martemucci, Grenoble (FR); François Rummens, Grenoble (FR); Elisa Vianello, Grenoble (FR); and Tifenn Hirtzlin, Grenoble (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Oct. 11, 2023, as Appl. No. 18/379,132.
Claims priority of application No. 22306587 (EP), filed on Oct. 20, 2022.
Prior Publication US 2024/0135979 A1, Apr. 25, 2024
Prior Publication US 2024/0233794 A9, Jul. 11, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A data storage circuit (MEM) comprising:
a first memory array (MEMFE) comprising a plurality of FeRAM memory units;
a second memory array (MEMOx) comprising a plurality of OxRAM memory units;
each of the first and second memory arrays (MEMFE, MEMOx) comprising: a plurality of word lines (WLi,Ox, WLj,Fe), a plurality of source lines (SLi,Ox, SLj,Fe) and a plurality of bit lines (BLj,ox, BLj,Fe);
for each column (Cj,ox, Cj,Fe) each memory unit (MUox,ij MUFe,ij) comprising:
a memory cell (MCOx, MCFe) having a first electrode (EL1, EL1′) and a second electrode (EL2, EL2′) connected to the source line (SLj,Ox, SLj,Fe) associated to said memory unit;
a selection transistor (T1) having a gate connected to the word line (WLi,ox, WLi,Fe) associated to said memory unit and placed in series with the memory cell between the source line (SL) and a bit line (BLj,ox, BLj,Fe) associated to of said memory unit;
said data storage circuit (MEM) comprising further:
a data transfer stage (TR) configured to transfer data from a set of source FeRAM memory units (MUFe,ij) having a common bit line (BLj,Fe) to a target OxRAM unit (MUox,ij) by converting a read signal (VBj,Fe) from said common bit line (BLj,Fe) to a transfer voltage (VTR) applied on a target line of the target OxRAM unit (MUox,ij), said target line corresponding to the word line (WLi,ox) or the source line (SLj,ox) and having the same direction as said common bit line (BLj,Fe).