US 12,394,459 B2
Semiconductor apparatus including a plurality of clock paths and a semiconductor system using the same
Ji Hyo Kang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 9, 2023, as Appl. No. 18/446,946.
Claims priority of application No. 10-2022-0179292 (KR), filed on Dec. 20, 2022.
Prior Publication US 2024/0203469 A1, Jun. 20, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1072 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor apparatus including a plurality of clock paths, the semiconductor apparatus comprising:
a first clock path configured to buffer a system clock signal pair to generate a first clock signal pair in a first operation mode;
a second clock path configured to multiply a frequency of the system clock signal pair to generate a second clock signal pair in a second operation mode;
a third clock path configured to convert the system clock signal pair to a Complementary Metal-Oxide-Semiconductor (CMOS) level to generate a third clock signal pair in a third operation mode;
a first selecting circuit configured to output, as a first reference clock signal pair, one of the first clock signal pair, the second clock signal pair, and the third clock signal pair according to the operation mode; and
a multi-phase clock generating circuit configured to generate first internal clock signals from the first reference clock signal pair.