US 12,394,454 B2
Time-division multiplexing for superconducting memory
William Robert Reohr, Severna Park, MD (US); and Benjamin Bogan Reohr, Severna Park, MD (US)
Assigned to William Robert Reohr, Severna Park, MD (US)
Filed by William Robert Reohr, Severna Park, MD (US); and Benjamin Bogan Reohr, Severna Park, MD (US)
Filed on Nov. 23, 2022, as Appl. No. 17/993,543.
Claims priority of provisional application 63/282,844, filed on Nov. 24, 2021.
Claims priority of provisional application 63/322,694, filed on Mar. 23, 2022.
Prior Publication US 2024/0005968 A1, Jan. 4, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 11/44 (2006.01); H03K 3/38 (2006.01); H03K 19/195 (2006.01)
CPC G11C 7/1066 (2013.01) [G11C 7/1063 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 11/44 (2013.01); H03K 3/38 (2013.01); H03K 19/1952 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells, the memory output circuit comprising:
a plurality of datum inputs adapted to operably receive a corresponding plurality of memory state signals from physically adjacent bit lines in the memory array;
at least one logic gate configured to implement logical OR functionality, the logic gate including a plurality of inputs, adapted to receive at least a subset of the plurality of datum inputs operatively coupled thereto, and an output adapted to propagate at least one datum output signal; and
at least one delay element operatively coupled to a corresponding one of the plurality of datum inputs, the delay element being configured to generate an output signal operably connected to a corresponding one of the plurality of inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.