US 12,394,450 B2
Integrated assemblies having shield lines between neighboring transistor active regions
Marcello Mariani, Milan (IT); and Antonino Rigano, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 27, 2023, as Appl. No. 18/114,692.
Application 18/114,692 is a continuation of application No. 16/667,289, filed on Oct. 29, 2019, granted, now 11,636,882.
Prior Publication US 2023/0206959 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/00 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H10B 12/00 (2023.01)
CPC G11C 5/005 (2013.01) [G11C 5/025 (2013.01); G11C 5/063 (2013.01); H10B 12/315 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An integrated assembly, comprising:
conductive lines supported by a base and extending along a first direction; some of the conductive lines being digit lines and a plurality of the conductive lines being shield-connection-lines;
semiconductor pillars over the digit lines; each of the semiconductor pillars comprising a channel region between an upper source/drain region and a lower source/drain region; the lower source/drain regions being coupled with the digit lines;
wordlines extending along a second direction which crosses the first direction; the wordlines including gate regions adjacent the channel regions; and
shield lines extending along the second direction; each of the shield lines being coupled with an associated one of the shield-connection-lines.