US 12,394,384 B2
Display panel and display device
Mengmeng Zhang, Wuhan (CN)
Assigned to Wuhan Tianma Microelectronics Co., Ltd., Wuhan (CN); and Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai (CN)
Filed by Wuhan Tianma Microelectronics Co., Ltd., Wuhan (CN); and Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai (CN)
Filed on May 1, 2024, as Appl. No. 18/652,392.
Claims priority of application No. 202310914871.3 (CN), filed on Jul. 24, 2023.
Prior Publication US 2024/0282268 A1, Aug. 22, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3275 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A display panel, comprising a first display region and a second display region, wherein the first display region comprises a first pixel row, the second display region comprises a second pixel row, a number of pixels in the first pixel row is a, and a number of pixels in the second pixel row is b, wherein 0<a<b;
the display panel further comprises a first scan control circuit, a second scan control circuit, a first scan line, and a second scan line, wherein the first scan line is electrically connected to the pixels in the first pixel row and one first scan control circuit, and the second scan line is electrically connected to the pixels in the second pixel row and two second scan control circuits; and
the first scan control circuit comprises a first output transistor, and the second scan control circuit comprises a second output transistor; wherein
in a case where a ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is within a first preset range, a ratio of a channel width-to-length ratio of the first output transistor to a channel width-to-length ratio of the second output transistor is a first ratio; and
in the case where the ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is within the first preset range, the first ratio R1 is:

OG Complex Work Unit Math
wherein α denotes a transistor process error parameter.