US 12,394,370 B2
Display device operated in single frequency mode and multi-frequency mode
Jaekeun Lim, Yongin-si (KR); Bon-Seog Gu, Yongin-si (KR); Sangan Kwon, Yongin-si (KR); Soon-Dong Kim, Yongin-si (KR); Jinyoung Roh, Yongin-si (KR); and Hae-Kwan Seo, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Jun. 11, 2024, as Appl. No. 18/740,025.
Application 18/740,025 is a continuation of application No. 18/142,237, filed on May 2, 2023, granted, now 12,033,568.
Claims priority of application No. 10-2022-0064847 (KR), filed on May 26, 2022.
Prior Publication US 2024/0331623 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device, comprising
a display panel including a plurality of pixels, each including a pixel circuit and a light emitting element, a plurality of scan lines connected to the pixel circuit, and a data line connected to the pixel circuit,
wherein the pixel circuit includes:
a first capacitor connected to a first node and a second node opposite to the first node;
a first circuit portion including a first transistor including a gate electrode, a first electrode electrically connected to the data line, and a second electrode electrically connected to the first node; and
a second circuit portion connected to the second node and the light emitting element,
wherein, during a period right before the light emitting element emits light, a reference voltage is provided to the second electrode of the first transistor and an electrical connection between the second electrode of the first transistor and the first node is disconnected,
wherein the first circuit portion further includes a second transistor connected between the second electrode of the first transistor and a reference voltage line to which the reference voltage is provided, and
wherein the second circuit portion includes a third transistor connected between the second node and a first initialization voltage line to which a first initialization voltage is applied.