US 12,394,365 B2
Pixel circuit and driving method thereof, and display panel and driving method thereof
Li Xiao, Beijing (CN); Haoliang Zheng, Beijing (CN); Minghua Xuan, Beijing (CN); Seungwoo Han, Beijing (CN); Hao Chen, Beijing (CN); Dongni Liu, Beijing (CN); Jiao Zhao, Beijing (CN); Liang Chen, Beijing (CN); and Qi Qi, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Dec. 8, 2023, as Appl. No. 18/533,211.
Application 18/533,211 is a continuation of application No. 17/636,897, granted, now 11,875,734, previously published as PCT/CN2021/088615, filed on Apr. 21, 2021.
Prior Publication US 2024/0185772 A1, Jun. 6, 2024
Int. Cl. G09G 3/32 (2016.01); G09G 3/20 (2006.01); G09G 3/3208 (2016.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 3/2007 (2013.01); G09G 3/3208 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/043 (2013.01); G09G 2320/045 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A drive method for a display panel, wherein:
the display panel comprises: pixel circuits arranged in array, a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line;
the pixel circuits are respectively connected with the current data lines and the time-length data lines, at least one current data line is connected with the first current selection signal line or the second current selection signal line, two adjacent current data lines are connected with different current selection signal lines, at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line, and two adjacent time-length data lines are connected with different time-length selection signal lines;
the method comprises: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line; and
time for at least two signal lines of the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line to receive the valid level signal is not overlapped;
wherein:
the display panel further comprises: a reset signal line, a scanning signal line, and a light-emitting signal line, the pixel circuits are respectively connected with the reset signal line, the scanning signal line and the light-emitting signal line;
the method further comprises: providing a valid level signal to the reset signal line, the scanning signal line and the light-emitting signal line; and
time for at least two signal lines of the reset signal line, the scanning signal line and the light-emitting signal line connected to a same pixel circuit to receive the valid level signal is not overlapped;
wherein: the time for the reset signal line connected to a (m+1)th row of pixel circuits to receive the valid level signal is within the time for the light-emitting signal line connected to a mth row of pixel circuits to receive the valid level signal, and 1≤m≤M and M is a total number of rows of the pixel circuits.