US 12,393,759 B2
Integrated circuit layouts with fill feature shapes
Yu-Cheng Yeh, New Taipei (TW); Yen-Sen Wang, Hsinchu (TW); and Ming-Yi Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 16, 2022, as Appl. No. 17/745,224.
Application 17/745,224 is a continuation of application No. 15/637,484, filed on Jun. 29, 2017, granted, now 11,334,703.
Prior Publication US 2022/0277128 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H10D 89/10 (2025.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); H10D 89/10 (2025.01); G06F 30/394 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
initializing an integrated circuit layout, wherein the initializing of the integrated circuit layout includes defining design rules associated with the integrated circuit layout, and the design rules includes a first set of design rules governing spacing of Front-End Of Line (FEOL) shapes and a second set of design rules governing spacing of Back-End Of Line (BEOL) shapes;
inserting, into the integrated circuit layout, a design containing a first set of FEOL shapes of an integrated circuit and a first set of BEOL shapes of the integrated circuit;
inserting, into the integrated circuit layout, a set of cells containing a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit, wherein the second set of FEOL shapes includes contact shapes that define contacts of the integrated circuit, wherein the set of cells does not cover an entirety of the integrated circuit layout, wherein the set of cells are inserted in a way such that the first set of design rules is satisfied but the second set of design rules is violated with conflicts in the first and second sets of BEOL shapes but free of conflicts in the first and second sets of FEOL shapes;
after the inserting of the set of cells into the integrated circuit layout, removing a subset of the second set of BEOL shapes that conflict with the design, while the second set of FEOL shapes remains;
after the removing of the subset of the second set of BEOL shapes, inserting, into the integrated circuit layout, at least a third set of BEOL shapes, wherein the third set of BEOL shapes overlaps with at least one of the cells, wherein a removed one in the subset of the second set of BEOL shapes is previously positioned in a first BEOL layer of the integrated circuit, and wherein at least one of the third set of BEOL shapes that overlaps with the at least one of the cells and at least a remaining one of the second set of BEOL shapes inside the at least one of the cells are both positioned in the first BEOL layer; and
providing the integrated circuit layout that includes the design, the set of cells, and at least the third set of BEOL shapes for fabrication of the integrated circuit.