US 12,393,545 B2
Automatic high-speed shutdown for C-PHY receiver
Yasser Ahmed, San Diego, CA (US); Sachin Ajit Devamare, San Diego, CA (US); and Vinaya Ajjampura Rajappa, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 5, 2023, as Appl. No. 18/460,905.
Prior Publication US 2025/0077461 A1, Mar. 6, 2025
Int. Cl. G06F 13/42 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 2213/0016 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An interface circuit, comprising:
a data recovery circuit configured to decode data from a stream of symbols received over three wires of a serial bus according to a high-speed mode defined by a Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol;
a protocol interface circuit coupled to an output of the data recovery circuit and configured to receive decoded data from the data recovery circuit, and further configured to generate a first end-of-transmission (EOT) signal that indicates whether data transmission has been completed; and
a finite state machine configured to cause the data recovery circuit to be disabled when the first EOT signal indicates that data transmission has been completed.