US 12,393,531 B2
Quad-channel DRAM
Steven C. Woo, Saratoga, CA (US); and Torsten Partsch, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Aug. 7, 2023, as Appl. No. 18/231,108.
Application 18/231,108 is a continuation of application No. 17/433,071, granted, now 11,762,787, previously published as PCT/US2020/018634, filed on Feb. 18, 2020.
Claims priority of provisional application 62/811,903, filed on Feb. 28, 2019.
Prior Publication US 2024/0028527 A1, Jan. 25, 2024
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) 20 Claims
OG exemplary drawing
 
1. A packaged dynamic random access memory (DRAM), comprising:
a rectangular array of electrical connection conductors, the electrical connection conductors grouped into first, second, third, and fourth quadrants to serve as external, to the packaged DRAM, electrical connection points for a first memory channel, a second memory channel, a third memory channel, and a fourth memory channel, respectively; and
mode indicator circuitry to specify at least first and second modes wherein, in the first mode, each of the first, second, third and fourth memory channels are are to each concurrently operate memory channel command, address, and data transfer functions independent of the other concurrently operating first, second, third, and fourth memory channels, and in the second mode, the first and third memory channels are to each concurrently operate memory channel command, address, and data transfer functions independent of the other concurrently operating first and third memory channels, and also in the second mode, the second and fourth memory channels are disabled.