US 12,393,479 B1
Exception event handling in flash memory system
Santhosh Reddy Akavaram, Hyderabad (IN); Sai Naresh Gajapaka, Hyderabad (IN); Radhakrishna Mugada, Hyderabad (IN); Chintalapati Bharath Sai Varma, Hyderabad (IN); and Sridhar Anumala, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 21, 2024, as Appl. No. 18/670,511.
Int. Cl. G06F 11/07 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 11/073 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller of a host device configured to couple the host device to a memory system through a memory interface, the memory controller configured to perform operations including:
receiving, by the memory controller of the host device, a response from the memory system, the response comprising user data, an indication that an exception event was encountered by the memory system, and information regarding the exception event encountered by the memory system; and
transmitting, by the memory controller of the host device to the memory system, an acknowledgement of receiving the indication that the exception event was encountered by the memory system.