US 12,393,467 B2
Data processing method and apparatus, distributed data flow programming framework, and related component
Hongwei Kan, Jiangsu (CN); Nan Wu, Jiangsu (CN); Rengang Li, Jiangsu (CN); and Yanwei Wang, Jiangsu (CN)
Assigned to INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 17/781,317
Filed by INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Apr. 27, 2020, PCT No. PCT/CN2020/087157
§ 371(c)(1), (2) Date May 31, 2022,
PCT Pub. No. WO2021/155642, PCT Pub. Date Aug. 12, 2021.
Claims priority of application No. 202010080853.6 (CN), filed on Feb. 5, 2020.
Prior Publication US 2023/0004433 A1, Jan. 5, 2023
Int. Cl. G06F 9/50 (2006.01); G06F 15/173 (2006.01)
CPC G06F 9/505 (2013.01) [G06F 15/17331 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A data processing method, for applying to a host side, wherein the host side is connected to a Field Programmable Gate Array (FPGA) accelerator side, the FPGA accelerator side comprises a plurality of FPGA acceleration boards, and the plurality of FPGA acceleration boards are connected to each other through a network, the data processing method comprises:
dividing, by the host side, a data processing task into a plurality of data processing subtasks, and determining target FPGA acceleration boards in the FPGA accelerator side corresponding to each of the plurality of data processing subtasks;
selecting a first target FPGA acceleration board and a second target FPGA acceleration board from all of the target FPGA acceleration boards;
sending all of the plurality of data processing subtasks and task distribution information to the first target FPGA acceleration board, and sending all of data to be computed and data distribution information to the second target FPGA acceleration board: wherein the task distribution information comprises correspondences between the plurality of data processing subtasks and the target FPGA acceleration boards, and the data distribution information comprises correspondences between the data to be computed and the target FPGA acceleration boards;
sending, by the first target FPGA acceleration board, the plurality of data processing subtasks to corresponding target FPGA acceleration boards according to the task distribution information, and sending, by the second target FPGA acceleration board, the data to be computed to corresponding FPGA acceleration boards according to the data distribution information; and
executing a corresponding data processing subtask of the plurality of data processing subtasks by each of the target FPGA acceleration boards to obtain a data processing result, wherein the data processing result comprises intermediate computing data or a final processing result of the data processing task, source data of each of the plurality of data processing subtasks comprises at least one of the data to be computed or the intermediate computing data, and the intermediate computing data is transmitted through the network between the target FPGA acceleration boards.