| CPC G06F 9/5044 (2013.01) [G06F 9/485 (2013.01); G06F 9/5016 (2013.01); G06F 9/505 (2013.01)] | 20 Claims |
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1. A method comprising:
assigning a plurality of threads to a hardware pipeline that contains a sequence of hardware stages that include: a computing stage, a suspending stage, and a resuming stage, wherein:
each cycle of the hardware pipeline can concurrently execute a respective distinct stage of the sequence of hardware stages for a respective distinct thread of the plurality of threads, and
a read of a random access memory (RAM) can be requested for a thread of the plurality of threads only during the suspending stage;
while a previous state of a plurality of states of a finite state machine that implements a coroutine of the thread of the plurality of threads is in the suspending stage of the sequence of hardware stages:
requesting a read of the RAM, and
unconditionally suspending the thread;
while the coroutine of the thread is in the resuming stage of the sequence of hardware stages, correlating an asynchronous response from the RAM to: the thread and a next state of the plurality of states of the finite state machine; and
while in the computing stage of the sequence of hardware stages, the next state of the plurality of states of the finite state machine executing based on the asynchronous response from the RAM.
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