US 12,393,428 B2
Self-scheduling threads in a processor based on a threshold associated with pipeline stages
Tony Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 10, 2023, as Appl. No. 18/378,281.
Application 18/378,281 is a continuation of application No. 17/075,399, filed on Oct. 20, 2020, granted, now 11,803,391.
Prior Publication US 2024/0086200 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/48 (2006.01); H01L 25/065 (2023.01); G06F 15/78 (2006.01)
CPC G06F 9/3851 (2013.01) [G06F 9/3836 (2013.01); G06F 9/3867 (2013.01); G06F 9/48 (2013.01); G06F 9/4887 (2013.01); H01L 25/0655 (2013.01); G06F 15/7825 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A computer processor comprising:
a pipeline including a fixed number of stages;
a scheduler to schedule thread instructions for the computer processor, wherein the scheduler includes a ready-to-run queue, the ready-to-run queue configured to order thread IDs to schedule execution of corresponding threads on the pipeline;
first circuitry to:
detect that an instruction in a thread executing on the computer processor will not complete within the fixed number of stages of the pipeline; and
pass a thread identifier (ID) of the thread along with a request, corresponding to the instruction, to an entity external to the computer processor, wherein, to pass the thread ID, the thread ID is absent from the scheduler and the pipeline; and
second circuitry to:
receive a response to the request, the response including the thread ID; and
providing the thread ID from the response to the scheduler to reschedule the thread on the computer processor, wherein the computer processor is configured to execute the thread based on the thread being rescheduled.