US 12,393,427 B2
Core-based speculative page fault list
Toby Opferman, Portland, OR (US); Michael W. Chynoweth, Placitas, NM (US); Rajshree A. Chabukswar, Sunnyvale, CA (US); and Vijay C. Bahirji, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,944.
Prior Publication US 2023/0091167 A1, Mar. 23, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3861 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
an instruction decoder comprising first circuitry to decode one or more instructions to be executed by a core of a processor which is to include the integrated circuit; and
second circuitry coupled to the instruction decoder, the second circuitry to:
determine if a decoded instruction involves a page to be fetched;
determine one or more hints for one or more optional pages that are subject to being fetched along with the page for the decoded instruction; and
provide the one or more hints to a page fault handler that is to be executed with the core;
wherein:
the one or more hints comprise:
a speculative size of memory that is subject to being fetched for one or more of:
the page to be fetched; and
an optional page that is subject to being fetched; and
a speculative page fault list of speculative addresses of pages that are subject to being fetched together with respective speculative sizes for an address of the page to be fetched for the decoded instruction and the speculative addresses; and
the speculative size is greater than a single page size.