US 12,393,367 B2
Lean command sequence for multi-plane read operations
Naveen Vittal Prabhu, Folsom, CA (US); Aliasgar Madraswala, Folsom, CA (US); Sandeep Rasoori, Folsom, CA (US); and Trupti Bemalkhedkar, San Jose, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,899.
Prior Publication US 2023/0062668 A1, Mar. 2, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
generate address information for a plurality of planes in NAND memory;
exclude column addresses from the address information;
send a read command sequence to the NAND memory, wherein the read command sequence includes the address information; and
exclude plane confirm commands and busy cycles from the read command sequence.