US 12,393,345 B2
Maximum row active time enforcement for memory devices
Donald M. Morgan, Meridian, ID (US); and Bryan David Kerstetter, Kuna, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,998.
Claims priority of provisional application 63/479,168, filed on Jan. 9, 2023.
Prior Publication US 2024/0231635 A1, Jul. 11, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 11/406 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/40603 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host device comprising a first controller; and
a memory device comprising:
a plurality of memory banks configured to store data;
a second controller configured to:
receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks;
activate, in response to the activate command, the first memory bank of the plurality of memory banks; and
a circuit configured to:
determine whether a first precharge command to close the first memory bank has been issued by the first controller within a maximum threshold amount of time since issuance of the activate command issued by the first controller; and
internally issue, within the memory device, a second precharge command to close the first memory bank if the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.