	US 12,393,344 B2
	Apparatuses and methods for die replacement in stacked memory
Scott Eugene Smith, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 24, 2021, as Appl. No. 17/210,885.
Claims priority of provisional application 63/006,180, filed on Apr. 7, 2020.
Prior Publication US 2021/0311638 A1, Oct. 7, 2021
Int. Cl. G06F 11/00 (2006.01); G06F 3/06 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01)

CPC G06F 3/0614 (2013.01) [G06F 3/0653 (2013.01); G11C 29/12 (2013.01); G11C 29/787 (2013.01)]

30 Claims

1. An apparatus comprising:

a memory die electrically decoupled from and electrically couplable to at least one of a logic die or one or more other memory dies, the memory die comprising an enable/disable die circuit configured to electrically couple the memory die, responsive to a signal received via the at least one of the logic die or the one or more other memory dies, indicating the memory die is to be electrically coupled to the at least one of the logic die or the one or more other memory dies,

wherein the enable/disable die circuit is configured to electrically couple the memory die to the at least one of the logic die or the one or more other memory dies by programming one or more antifuses.

12. An apparatus comprising:

a master die;

a slave die electrically coupled to the master die; and

a spare die electrically decoupled from the master die and electrically couplable to the master die,

wherein each of the master die, the slave die, and the spare die include an enable/disable die circuit, wherein the enable/disable die circuit included with the slave die is configured to electrically decouple the slave die from the master die by programming one or more fuses or one or more switches responsive to a signal and the enable/disable die circuit included with the spare die is configured to electrically couple the spare die to the master die by programming one or more antifuses or one or more switches responsive to the signal,

wherein the spare die is accessed for a memory operation directed to the slave die responsive to the signal, and

wherein each of the master die and the slave die further include a master/slave designation circuit, wherein the master/slave designation circuit is configured to disable one or more components of the slave die when the slave die is designated as the slave die.

19. A method comprising:

detecting a defective memory die of a stack of memory die, wherein the stack of memory die and the defective memory die operate together at a memory capacity;

electrically disabling the defective memory die from the stack of memory die by programming one or more fuses; and

electically enabling a spare die of the stack of memory die to the stack of memory die by programming one or more antifuses,

wherein the spare die is accessed for a memory operation directed to the defective memory die responsive to electrically disabling the defective memory die and electrically enabling the spare die and wherein the stack of memory die and the spare die operate together at a same memory capacity when the spare die is electrically enabled and the defective memory die is electrically disabled.

25. A method comprising:

performing a self-test on a memory die of a stack of memory die to generate a result;

providing a defective die signal based on the result indicating the memory die is defective;

electrically decoupling, by programming one or more fuses or one or more switches, the memory die from the stack of memory die responsive to the defective die signal; and

electrically coupling, by programming one or more antifuses or switches, a spare die of the stack of memory die to the stack of memory die,

wherein the stack of memory die operates together with the spare die at a same capacity with the spare die electrically coupled as the stack of memory die operates together with the memory die electrically coupled.